Shift-register employing rows of flipflops having serial input and output but with parallel shifting between rows



March 16, 1965 R. A. URBAN 3,174,106

SHIFT-REGISTER EMPLOYING ROWS OF' FLIP-FLOPS HAVING SERIAL INPUT AND OUTPUT BUT WITH PARALLEL SHIF'TING BETWEEN ROWS Filed Dec. 4, 1961 3 Sheets-Sheet l INPUT OS- l N OSCIL- LATOR TIME March 16, 1965 R A, URBAN 3,174,106

SHIFT-REGISTER EMPLOYING ROWS OF FLIP-FLOPS HAVING SERIAL INPUT AND OUTPUT BUT WITH PARALLEL SHIFTING BETWEEN ROWS Filed DSG. 4, 1961 3 SheetS-Shee 2 Nygz" lbn uln

non

non

non

non

non

March 16, 1965 R. A. URBAN 3,174,106

SHIFT-REGISTER EMPLOYING ROWS OF FLIF-FLOPS HAVING SERIAL INPUT AND OUTPUT BUT WITH PARALLEL SHIFTING BETWEEN ROWS Filed Deo. 4, 1961 3 Sheets-Sheet 3 United States Patent (Y SIET-REGISTER EMPLOYING ROWS F FLIP- FLOPS HAVING SERIAL INPUT AND OUTPUT BUT WITH PARALLEL SHIFTING BETWEEN RWS Roger A. Urban, St. Paul, Minn., assignor to Sperry Rand Corporation, New York, N.Y., a corporation of Delaware Filed Dec. 4, 1961, ser. No. 159,199 14 Claims. (Cl. 328-37) This invention relates to shift registers which are composed of a plurality of bistable devices or stages and more particularly to that class of shift registers which utilizes transistors in each stage.

The use of shift registers which are capable of storing information in binary form and of selectively manipulating such information in response to applied control signals is well known in the computation and control art. Such registers consist of a plurality of bistable devices each of which may be defined as a device which is capable of being placed in either one of two stable states and which bistable device usually includes two input terminals and two output terminals, one of each of which is associated with one of its two states. As is well known, a bistable device has the characteristic that it will remain in either one of its two states until caused to change to the other state by the application of a signicant signal upon the input terminal of the other of its then occurring states. Each bistable device has two substantially difierent output signal levels which are affected by the imposition of one of the two corresponding input signals upon the respective input terminal with the corresponding signais arbitrarily designated as representing a 0 or 1.

The shift register disclosed herein is an electronic circuit consisting of a series of bistable devices or stages, each stage adapted to register a 0 or a 1, i.e., emit a 0 or a 1" from the set side of the stage. The circuit on actuation by a control signal causes each stage, or group of stages, to impose upon the next succeeding stage, or group of stages, the condition that was in itself prior to initiation of the controlling signal. Essentially, the invention disclosed herein provides an apparatus wherein discrete bits of an input data word are serially entered into a iirst group of bistable devices. The data stored in the first group of bistable devices is then parallel shifted group-by-group to successive groups of bistable devices until the data is entered into the last group from which the data is serially exited.

The diierent positions of the bits of the input data word are normally assigned increasing significance which with the use of the binary arithmetic system represent the ascending power of '2, i.e., the rst bit being 20 and the last bit being 2b where b+1=the number of bits in the word, or the word length. These binary numbers or digits are then represented by reference to the state of each stage of the series of stages, one state being a "0 and the other state being a 1. In the embodiment of FIG. 1 the true of the input data word is stored in the 1 or set side of the stage while the complement is stored in the 0 or clear side. Thus the true of the input data word is stored in and successively transmitted from stage-to-stage by the set side of each stage while the complement is stored in and successively transmitted from stage-to-stage by the clear side of the stage. Further, the complement of the data may be achieved in the set or true side of each stage by the simple inversion of the state of each stage in which the 0 s are changed to "1 s and the 1 s are changed to 0s. Additionally, data may be entered directly into each stage by imposing a significant signalin the embodiment of FIG. 1 said signal is representative of a l-on the appropriate input terminal.

3,174,105 Patented Mar. 16, 1965 ICC In the past it has been necessary to provide some means of preventing the race problem in which the bistable device of a given stage reacts to a given input signal prior to the cessation of the application of an output signal to the next succeeding stage. These means have included delay circuits which have been incorporated in the input circuit of the output circuits of the bistable devices of each stage of the register. When delay circuits are used it is also necessary to limit the width of the controlling sigual such that such signal is less than the delay provided by such means. If such precautions are not provided thc information stored in the register may be shifted more than one stage during each application of the controlling signal. The shift register disclosed herein provides a novel method of gating information to successive stages, or groups of stages, within the shift register so as to preclude the possibility that a given stage may accept an input signal at the same time that it is impressing an output signal upon a successive stage which condition, if allowed, would permit the input data to be transmitted to the next successive stage, or groups of stages, with the resultant loss of data significance.

The idealized concept of a digital computer consists of four basic units: arithmetic, control, memory and inputoutput. In the arithmetic unit there are temporary storage locations or registers which receive data words from the memory unit. As the data word is transmitted from the memory unit to an arithmetic register or back again it passes through logical gating networks. In these gating networks the data are transformed or manipulated according to the operation being executed as determined by ythe control unit. Thus, it is possible to conceive of a digital computer as consisting of a temporary storage means and a permanent storage means with gating networks in between. When data words are transmitted from the permanent storage means, the computer memory, through the gating networks to the temporary storage means, the arithmetic unit registers, and then back again to the gating networks, two general methods of transmitting the data words are utilized. These methods are designated as serial or parallel transmission with the term serial or parallel designating the type of digital computer involved. ln a serial computer the word is transmitted serially, in a train, one bit at a time to and from the computers memory through the gating networks. The length of time during which one bit is transmitted from the memory through the gating networks and into the register is called a bit time, or unit time, interval. Thus. if a word has L bits, it would take L bit time intervals to transmit this data word through an arithmetic register from the computers memory or back. In contrast, in a parallel computer the bits of a data word can be transmitted through the gating networks from the computers memory to an arithmetic register or back simultaneously, or in parallel. Thus it takes only one bitrtime interval to transmit an entire data Word from the computers memory to the arithmetic registers through the gating networks. It is apparent then that parallel computers are many times faster than serial computers. However, this increased speed is obtained at a cost of considerably more hardware; for a serial computer is required to handle only one bit at a time Whereas a parallel computer is required to handle all the bits of the data word simultaneously. Thus a serial computer will be considerably less expensive but slower than a parallel computer. It is thus apparent that in applications where extremely fast manipulative speeds are not essential, it is expedient to utilize a serial computer, thus providing a computer with an optimum of utility and a minimum of cost.

The apparatus `as disclosed herein provides a shift register which affords a plurality of uses in a serial computer. One use is as a dynamic storage device or a dynamic delay line in which a delay of Lbit times, where L equals the number of bits in the data word, or word length, is accomplished. Additionally, byproviding additional circuit means for imposing discrete signals upon selected stages, parallel readin yof a data word may be achieved to create in effect a parallel-.to-serial converter. Also additional circuit means for transmitting discrete signals from selected stages may be added to create in effect a serialtoparallel converter. Further, it is apparent to one skilled in the art that the arrangement of the bistable devices or stages into groups of stages may be of a variety :of combinations so as to transmit in parallel certain bit combinations peculiar to a variety of number systems. Thus the embodiment of FIG. 1 utilizes groups of three stages per group so as to accomplish a parallel shift of octal characters,ri.e., three binary bits make up one octal character. It then follows that groups of four stages per group could be utilized-to accomplish a parallel shift of a binary coded decimal character of four bits. Further, groups of six stages per group could be utilized to accomplish a parallel shift of a Flexowriter coded character of siX bits. Another use of the above suggested additional circuit means for imposing discrete signals upon selected stages would be to permit the entry of bits of data into a preselected stage or to complement data already stored in the preselected stage. It can thus be seen. that the invention disclosed herein has a myriad of uses with the embodiment of FIG. 1 being illustrative only with no limitation thereto intended.

A primary object of the present invention is to provide an apparatus for the dynamic delay of a data word consisting of la plurality of binary digits or bits.

Another object of this invention is to provide an apparatus which serially picks up a data Word consisting of a plurality of bits, shiftsgroups of said bits in parallel,

and then. emits said bits in serial.

Another object of this invention is to provide an apparatusrwhich consists of a plurality of bistable devices which ensures the parallel shifting of data in groups of bits'without the loss of data significance. Y

Another object of this invention is to provide an apparatus which has the capability of providing serial readin-serial readout, serial readin-parallel readout, parallel readin-serial readout, and parallel readin-parallel readout. Y

Another object of Ithis invention-is to provide an apparatus which has the capability of providing for the serial readin of a data wordy which consists of a plurality of multi-bit characters, dividing said word into said characters, and then to readout said characters in parallel.

A further object of this invention is to provide an apparatus which has the capability of dynamically storing a data word which consists ofV a plurality of bits.

A still further object of this invention is to provide an :apparatus which through the use of synchronized gating ignals avoids the race problem which is encountered in high'speed shift registers which utilize transistors as the active elements.

These and other more detailed and specific objectives will be disclosed in the courseV of the following specification, .reference being had to the accompanying Ydrawings in which:

FIG. l is a schematic diagram of one embodiment of this invention which illustrates a shift register that will serially accept a data word of bits in length, shift said Word in parallel in groups of three bits, and then emit said bits serially.

FIG. 2 is an illustration of the pulse timing -of the embodiment of FIG. 1.

FIG. 3 is an illustration of vthe movement of the bits of a 15 bit input data word as they are shifted through the shift register of FIG. l under control of the gating waveforms of FIG. 2.

The illustrated embodiment of FIG. l is a schematic diagram of an exemplary embodiment of this invention which advantageously employs conventional logic packages to provide a reliable high speed, low power shift register. This embodiment has the capability of serially accepting a data Word of l5 bits in length, shifting said word in parallel in octal groups of 3 bits per group and then emitting said bits serially.

AND circuits, AND-1 through AND-50, are conventional bistable devices which are well known in the art. As used in the illustrated embodiment of FIG. 1 a 1 is present at the output only when all the inputs are a 1. A 0 on any one or more inputs Will cause the output .to be a 0.

OR circuits, OR-l through OR-Z, are conventional OR circuits which are well known in the art. A 0 is present at the output only when all the inputs are 0. A l on any one or more inputs willY cause the output to be a 1.

FLIP-FLOP circuits, FF-l through F12-22, are conventional bistable circuits which are well known in the art. As is well known, a iiip-op is a device that temporarily stores a single bit, and correlatively its complement. Its outputs are voltage levels representative of either a 0 or a l with the established level remaining fixed until some change occurs at its inputs. Generally a flip-flop has two input terminals. A l on a first, or set, input tenninal will cause the output at the set output Yterminal to rise to the l signal level, a 1 on the other, or clear input terminal will causeV the output at the set output terminal -to fall to the 0 signal level. As usedin the illustrated embodiment of FIG. 1, a flip-flop is 'designated as having a pair of 0 or clear input and output terminals and a pair of 1. or set input and output terminals. If the flip-flop is set, i.e., with a 0 being emitted from the 0 or clear side and a l being emitted from the l or set side, impressing a l upon the clear side inputV terminal results in a l out of the clear side and a O out of the set side. Conversely, impressing a 1 on the set side input terminal results in a .1 being emitted from the set side and a O being emitted from the clear side. Further, l s on the Vinput terminals of the clear and the set sides must be mutually exclusive, i.e., there cannot be a 1 impressed upon the O or clear side and the 1 or set side simultaneously, or the final condition of the ip-op will be undeterminable.

Oscillator OS-l is of a conventional design which is well known in the art. It is triggered by a master clock, not shown, to be synchronized with the data word that is entered into shift register 8 through input means 9. The output, which consists of waveforms WF-a and WF-b of FIG. 2 is essentially a two phase signal of frequency F and of unit time T where T=1/F.

Ring Counter RC-l is of a conventional design which is well known in the art. It, upon imposition of WF-a and `VVF-b from oscillator OS-l, provides waveforms WF-c through WF-h of FIG. 2. Each of the Waveforms WF-c through WF-h are successively displaced a time T 2, where T =1/F, and have a frequency Z Where Zzthe frequency of WF-a divided by the number of devices of a group; lor Z=F/ 3, and a unit time S where S=the unit time of WF-a times the number of devices of a group, or S=3T. Additionally, :the pulse length and displacements of WF-c .through WF-lz are such as to cause such waveforms to overlap and to be coincident with certain predeterminedpulses of WF-a and WF-b, i.e., WF-a, pulse 1t) is coincident with WF-c, pulse 12; WF-b, pulse 14 is coincident with WF-d, pulse 16, etc. These relationships provide coincident pulses whose coincident characteristics provide -the gating function required to shift the signal of WF-k through shift register 8.

The embodiment of FIG. 1 is designed to accommodate a wordV of 15 bits in length wherein a l bit is represented by a pulse having a voltage level of -i-l volt and a 0 bit is represented by a pulse having a voltage level of ground potential with the time between successive bits,

or bit time, equal to T as shown in WF-k of FIG. 2. The time required for a word of bits to be entered into shift register 8 of FIG. 1 is thus l5 times the bit time or 15T. Additionally, the timing -of the chain of bits making up the input data word, for example WF-k, is synchronized by means not shown to he coincident in time with WF-a of FIG. 2 such that the bit of lowest significance, bit 2b, where 11:0, or pulse 18 of WF-k is impressed upon input terminal coincident with WF-a pulse 10 and WF-c, pulse 12 being impressed upon gate AND-2. Thus, at time t0 WF-a pulse 10, WF-c pulse 12, and WF-k pulse 18 which is bit 2U of the input data Word, are coincident at the input side of gate AND-2.

lt will be apparent to one skilled in the art that only 1s are transmitted from one stage to another. As the true and the complement are transmitted in parallel from each stage, and as a l must appear in either the true or the complement representations of the input data word it follows that a l is transmitted to the set side of the succeeding stage if the true representation is a 1, or a l is transmitted to the clear side of the succeeding stage if the true representation is a 0. It will be appreciated that the input data Word is comprised of a series of pulses of a significant voltage level representing a l or of an insignificant voltage level representing a 0. In the embodiment of FIG. 1 the signal representations of the input data Word consist of a basic signal of ground potential which is also the insignificant voltage level representing a 0 while a l is represented by a +1 volt pulse. Reference to WF-k of FIG. 2 which is a typical input data word configuration illustrates the true of the input data word while WF-l illustrates the complement. Comparison of WF-k to WF-l indicates that .the steady state condition of the representation of the input data word is a signal of ground potential While a l is represented by a +1 volt pulse and a 0 is represented by a signal of ground potential. However, it must be kept in mind that in the embodiment of FIG. 1 it is necessary that if a 0 of WF-k is to be transmitted through the set sides of the stages of shift register 8 a 1 of WF-l must be transmitted through the clear sides of the stages thereof. Thus, in describing the operation of shift register 8 it may be described as shifting a 0, but in fact the operation consists of the shifting of l s whether in the true or the complement of the input data word.

ln explaining the operation of the illustrated embodiment of FIG. 1 it will be best to assume a data Word of WF-k (and its complement WF-l) which is 0f such configuration as to exemplify a typical operation thereof as a shift register as employed in a serial computer in which the operation of shift register S is to perform a dynamic delay of the data word. Initially it is assumed that the gating signals of WF-a through WF-h are stabilized in conformance with FIG. 2 and that data word WF-k is synchronized as stated above by means not shown.

In an endeavor to clarify the explanation of the operation of the illustrated embodiment of FIG. 1 in the following discussion, it is assumed that all flip-flops are set to the clear state, i.e., the 0, or clear, sides of FF- through FF22 are emitting a 1 with the l, or set, sides emitting a 0 although it is to be understood that such condition is not required for the proper operation of shift register 8.

At time t0 WF-a achieves a voltage level of +1 volt representative of a logical l which l is impressed upon input terminal 32. This l is then conducted through lines 34, 36, 3S and 40 to the associa-ted AND gates and terminal 42 of ring counter RC-l. Currently, WF-b achieves a voltage level of ground potential representative of a logical 0 which 0 is impressed upon input terminal 33. A 0 is then conducted through lines 35, 37, 39 and 41 to the associated AND gates and terminal 43 of ring counter RC-1. Ring counter RC-1 emits pulse 12 of WF-c which is a l and which is conducted by way of line 44 to the associated AND gates and in particular to Ygates AND-1 and AND-2. Coincident with the imposition upon gates AND-1 and AND-2 of the 1 s from WF-a and WF-c, the rst bit of the input data word as represented by pulse 18 of WF-k-the bit of the 20 bit position-is impressed upon gates AND-2, AND-4 and AND-6 by way of lines 46 and 47 and input terminal 36. Simultaneously, the complement of the first bit of the input data word is impressed upon gates AND-1, AND3 and AND-5 by Way of lines 48 and 49 and terminal 31. Under these conditions as exemplified by FIG. 2, gate AND-2 is the only gate satisfied, having l inputs from VVF-a, WF-c and WF-k, and thus the l of WF-k is stored in the set side of FF-l.

At time t1 WF-a is a 0 which 0 is impressed upon the input terminal 32. As before, this 0 is conducted through lines 34, 36, 38 and 40 to the associated AND gates and terminal 42 of ring counter RC-l. Concurrently, WF-b is a l which is impressed upon input terminal 33. As previously stated, this l is conducted through lines 3S, 37, 39 and 41 to the associated AND gates and terminal 43 of ring counter RC-1. l Ring counter RC- emits pulse 16 of WF-d which is conducted by way of line Sti to Ithe associated AND gates. Under these conditions as exemplified by FIG. 2 no AND gate is satisfied by having a l impressed upon all its inputs. Consequently no iiip-iiop is set or cleared.

At time t2 WF-a is a l which l is impressed upon the associated'circuitry as in time to. Ring counter RC-l emits pulse 20 of WF-e which is :conducted by Way of line 52 to the associated AND gates and in particular gates AND-3 and AND-4. Coincident with the imposition upon gates AND-3 and AND-4 of the ls from WF-a and WFe the second bit of the input data Word as represented by pulse S4 of WF-k-the bit of the 2 bit position--is impressed upon gates AND-2, AND-4 and AND-6 by the associated :circuitry as in time to. Simultaneously, the complement of the second bit of the input data word is impressed upon gates AND-3 and AND-5 by the associated circuitry as at time to. Under these conditions as exempliiied yby FIG. 2, gate AND-4 is the only gate satisiied having "1 inputs from VVF-a, W'F-e and WF-k and thus the l of WF-k is stored in the set side of FF-Z.

At time t3 WF-a is a 0 which 0 is impressed upon input terminal 32. As before this 0 is conducted through lines 34, 36, 38 and 40 to the associated AND gates and terminal 42 of ring counter RC-l. Concurrently, WF-b is a l which is impressed upon input terminal 33. As previously stated, this l is conducted through lines 35, 37, 39 and 41 to the associated AND gates and terminal 43 of ring counter RC-l. Ring counter RC-l emits pulse 22 of WF-f which is conducted by way of line 56 to the associated AND gates. Under these conditions as eX- emplified by FIG. 2 no AND gate is satised by having a l impressed upon all its inputs. Consequently, no flipflop is set or cleared.

At time t4 WF-cz is a l which l is impressed upon the associated circuitry as a time to. Ring counter RC-l emits pulse 24 of WF-g which is conducted by way of line 58 to the associated AND gates and in particular to gates AND-S and AND-6. Coincident with the imposition upon gates AND-5 and AND-6 of the l s of WF-a and WF-g, the third bit 'of the input data word represented by pulse 60 of WF-k+the bit of the 22 bit position-is impressed upon gates AND-2, AND-4 and AND-6 yof the associated circuitry as at time to. Simultaneously, the complement of the third bit of the input data word is impressed upon gates AND-1, AND-3 and AND-5 by the associated circuitry as at time to. Under these conditions as exemplified by FIG. 2, gate AND-6 is the only gate satisfied having l inputs from WF-a, WF-g and VJF-k and thus the l of WF-k is stored in the set side of FF-3. At this time, between t4 Iand t5, bits 1, 2, and 3 of the input data word have been loaded into FF-l, FF-Z and Fil-3, respectively, of the register of FIG. 1.

' tively.

At time t5 WF-a is a 0 which "0 is impressed upon input tenminal 32. As before, this is conducted through lines 34, 36, 38 and 40 to the associated AND gates and terminal 42 of `ring counter RC-l. Concurrently, NF-b is a 1 Which l is impressed upon input terminal 33; As previously stated, this l is conducted through lines 35, 37,39 and 41 to the associated AND gates and in particular gates AND-7 through AND-12 and terminal 43 of RC-l. Ring counter RC-l emits pulse 26 of WF-h which isiconducted by way of line 62 to the associated gates AND-7 through AND-d2.. Under these conditions only gates AND-8, AND-10 and AND-12 are satislied having l inputs from W'E-b, WF-h fand theset sides of FF-l, FF- Z and FiF-3, respec- FF-Z and F1343 Vare loaded into the set sides of .FF-4, FF-S and F12-6, respectively.

At time t6 the circuit functions as described at time to are repeated with a 1 lrepresentativeof the fourth bit .of the .input data Word represented by pulse 64 of WF-kthe bit of ,the 23 bit position-being loadedinto the set side of FF-I through gate AND-2.V

At time t7 circuit functions as described at ime t1 are repeated with no flip-hops lbeing set or cleared.

At time t8 WF-a is a l which l is impressed upon Ring counter .RC-1 i the associated circuitry as attime to. emits pulse Zit Vof WF-e whichisconduoted by Way of line 52 to the associated AND gates andin particular gates AND-3 and AND-4. Coincident with the imposiv tion upon gates AND-3 and AND-4 of the "l s of WF-a fand WF-e the signal representative of lthe tth bit of the input data word-the bit of the 2^t bit position- Which isa signal :of ground potential, or a 0, is impressed upon gates AND-Z, AND-4 and AND-6 by the associa-ted circuitry as in time tu. Simultaneously, the complement of the fth bit of the input data word which is represented by pulse 67 of VVF-1, which is a 1, is

impressed upon gatesAND-l, AND-3 and AND-,5 by the associated circuitry as at Vtime to. Under these conditions as exemplified by FIG. 2, gate AND-3 i-s the only gate satisfied having "1 inputs of WF-a, WF-e and WF-1 `and thus the "l" of WF-l is stored in the clear'side of FF-Z. i Y

At time t9 circuit functions as described at time t3 are repeated with no flip-hops being set or cleared.

At time tm WF-a is a l which l is impressed upon the associated circuitry Ilas at time to.Y Ring counter RC-l emits pulse 24 of WF-g which is conducted by way of line 58 to gates AND-13 through AND-i8 and AND-5 and AND-6. Coincident with the imposition upon gates AND- and AND-6 of the l s from WF-a and WF-g, `the sixth bit of the input data'word represented by pulse 68 of WF-k-the bit'oiA the 25 bit position-is impressed upon gates ANDZ, ANDA and ANDAS by the associated circuitry as at time to. Under these conditions Ias exemplified by FIG. 2, gate AND-6 is the only gate satisfied having "1 inputs from WF-a, WF-g and WF-k and thus thefl lof WF-k is set into idF-6. As will be recalled in the above discussion, bits 1, 2 and 3 of the input data word which were 1s have been loaded into the set or 1 sides of FF-4, FF-S and FF6 at time 5. Thus at time im the set sides of F13-4,

FF-S and 12F-6, were impressing a l at gate AND-14 Y of F12-7, at gate AND-16 of FF-S, and at gate AN D-18 of FF-9, respectively. VUnder these conditions only gates AND-14, AND-i6 and AND-i8 are satisfied having 1 inputs from WF-a, WF-g and the set sides of 11F-4, FF-S and FF-, respectively. Thus the "1 s stored in the set sides of FF-4, FF-S and FF-6 are stored in the set side! of )FF-7, F1328, and FF-9, respectively.

At time tu WF-a is a 0which "0 is impressed upon input terminal 32. As before, this 0 is conducted through lines 34, 36, 3S, and 40 to the associated AND gates and terminal 42 of RC4. Concurrently, WFb is a "1 which l is impressed upon input terminal 33. As

Thus :the "1 s stored in the set sides of FPL-1,

Vof FF-S.

previously stated, this "1 is conducted through lines 35 37, 39, and 41 to the associated AND gates and in particular gates AND-'7 through AND-l2 and terminal 43 of ring counter RC4.. Ring counter RC-l emits pulse 26' of WF-Lh Whichis conducted by way of line 62 to the associated gates ANDJI' through. AND-12. As will be recalled in the above discussiombits 4 and 6 which were 1 s have been stored in the set side of FF-l and FF-3 and bit 5 which was a 0 has been stored in the clear side of FF-Z, prior to time tu Thus at time tu the set sides of FF-4 and FF-6Y were impressing a "l at gate AND-8 of ITF-4 and Vat gate AND-12 of 12F-6, respectively, and F-2 was impressing a l at gate AND-9 Under these conditions only gates AND-3, AND-12 and AND-9 are satisfied having l inputs from WF-b, WF-Iz and the set sides of FF-l and FiF-3 and the clear side of HL2, respectively. Thus the "1 stored in the set side of FF-l and FF-3 and the "0 stored in the clear side of FF-Z are stored in the respective sides of FF-4, FIF-6 and F13-5.

FIG. 3 illustrates the movement of bits of a 15-bit input'data word as they are shifted through the register of FiG. 1 under control of the gating waveforms of FIG. 2. This table as presented gives a clear picture of the status of the bits of the input'data word for each period of time beginning at the time to when the iirst bit of the input data word is impressed upon the associated gating circuits. As discussed above, near the conclusion of time tn andprior to time tlg, the Vfollowing bits of WF-k are As it is a characteristic of storage elements such as 'ip-flops FF-i through F12-22 to retain the stored information after it has Vbeen readout, the above example of the status of the bits of the input data words at a time greater than tu but less than tu indicates that the information read into F12-4, FF- and FF- is retained in FF-l,

- FF-Z and idF-3, respectively, after readout therefrom.

Thus, in interpreting FIG. 3 and in aiding al1-understanding of the how of data from left to right it is assumed that the data previously stored in a particular flip-flop is retained therein untilV destroyed by the reading of the succeeding data. For example, bit 4 is read into FF-l at time t6 and retained therein until time [12 when bit 7 is read therein with the resulting destruction of bit 4.

In a manner similar to that previously discussed, the bits of the input data word as exemplified by WFk are read into shift register 8 of FIG. l unt at a time irnmediately prior to time t30 when the following bits of `WF-k are stored in the corresponding flip-flops:

Table II B1t: Stored in 1 FF-16 2' FF-17 3 FF-IS 4 FF-13 5 FII-14 6 12F-15 7 F11-10 8 FF-ll 9 F12-12 10 FF-7 l1 FF-S 12 FF-9 13 FF-4 14 FF-S vl5 FF6 At time t3@ WF-a is a 1 which l is impressed upon the associated circuitry and in particular gates AND-37 through AND-42 as at time ta. Ring counter RC-l emits pulse 1c of WF-c which is conducted by Way of line 45 to the associated AND gates and in particular gates AND-37 through AND-42. As is illustrated in FIG. 3 bits l, 2, and 3 of the input data Word which were 1 s have been stored in the set sides of F11-16, FTF-17, and EF-18, respectively, prior to time [30 Thus at time t3@ the set sides of FIJ-16, idF-17, and 12F-118 were impressing a l at gate AND-38 of FF-, at gate AND-tl of FF-2, and at gate AND-42 of idF-21, respectively. Under these conditions only gates AND-38, AND-40 and AND-42, are satisfied, having l inputs from WF-a, WF-c and the set sides of FF-16, F13-17, and FF-l, respectively. Thus the ls stored in the set sides of the IFF-16, F13-17, and Fil-18 are stored in the set sides of Fri-19, FIS-2li, and FF-Zl, respectively.

At time tgl NF-b is a "1 which l is impressed upon the associated circuitry and in particular gates AND-61 through AND-36, AND-59 and AND-51B as at time t1. Ring Counter RC-l emits pulse 16 of VVF-d which is conducted by Way of line t? to the associated AND gates and in particular gates AND-31 through AND-3o, AND-43, and AND-a4. As is illustrated in PEG. 3, bits 4 and 6 which are l s have been stored in the set sides of EF-13 and 11F-15 and bit 5 which is a O has been stored in the clear side or" .FF-14 prior to time tgl. Thus at time tgl the set sides of 12F-13 and Fil-l5 are impressing a l at gates AND-32 of F13-16 and at gate AND-36 of FF-S and the clear side of TEF-14 is impressing a "1 at gate AND-33 of FF-i. Under these conditions gates AND-32, AND-35, and AND-33 are satisfied having l inputs from WF-b, WF-d and the set sides of FF- and idF-15 and the clear side of FF-lt, respectively. Thus the 1 stored in the set sides of FF-13 and TSF-15 and the l stored in the clear side of FF-14 are stored in the respective sides of idF-16, FiF-1S and ETF-17. Concurrently, the clear and set sides of idF-19, F13-2u and Fig-21 are impressing their contents on their respective gates AND-d3 through AND-4S. As gates AND-43 and AND-f1.4. are the only gates ANDed by WF-d, only the 1 stored in the set'side of FF- is passed through its respectivev gate AND-d4, to its respective gate Oil-2, and then to gate AND-5t! which is ANDed by the "1 of Wib by Way of line 76. Thus the 1 stored in the set side of FFA@ is impressed upon FF-ZZ which emits a 1" rom the set side thereof.

In a manner similar to that explained above and as illustrated in FIG. 3, it can be seen that at time taz the contents of FF-Ii, 12F-11, and TDF-12 are stored in Pif-13, idF-14, and IdF-1S, respectively.

In a manner similar to that illustrating the circuit functions at ltime tgl it can be seen that at time tag the contents of FF-Zti are stored in IdF-22 through the AND- ing action of WF-f at gates AND-45 and AND-46 and the ANDing action of WF-b at gates AND-49 and AND-5t). Additionally, and as illustrated in FIG. 3, the contents of FF-7, FF- and FF-9 are stored in F13-10, FiF-11, and FF-Z, respectively, through the ANDing action of VJF-b and WF-f at gates AND-19 through AND-Z4.

In a manner as explained above and as illustrated in PEG. 3, it can be seen that at time t3.; the contents of FiF-4, FF-S, and FF-e are loaded in FF-7, PF-S, and 12F-9, respectively.

In a manner similar to that illustrating the circuit functions at -time t31 it can be seen that at time 235 the contents of FF-Zl are stored in IFF-22 -through the AND- ing action of WF-h at gates AND-47 and AND-48 and the ANDing action of WF-b at gates AND-49 `and AND-Sil.

In a manner similar to that illustrating the circuit functions at time t3() through t35 it can be seen that the contents of FF-l through FF-l are successively shifted into higher ordered flip-flops until at successive occurrences of WF-b being a l the contents of F12-19, FF-Zt), and FiF-21 are stored in FF-ZZ, and consequently are emitted as -a train `of binary signals at a frequency determined by the frequency of WF-b, or at a -frequency of F: 1/ T.

It is apparent that upon a reading ofthe above description of the illustrated embodiment of FIG. 1, certain optimum relationships of the number of phases and frequencies of the signals involved and the particular configuration of bistable devices apply. Thus, i-t is apparent that the number of bits forming the input data word-if the register is to be capable of holding the entire Word, the number of bits of the input data word forming a group thereof and the frequency of the input data Word `determine the frequencies and number of phases of the clocking signals, the number of bistable devices per group and the number of groups per shift register. Thus, if an input data. Word consists of a serial :chain of L bits of a frequency F and of m bits per group, itis apparent that if Oscillator OS-l provides a phase signal of frequency F, ring counter RC-l should provide a mp phase signal of frequency F/m as illustrated in FIG. 2. Under these conditions and as discussed hereinbefore, the bits of the input data Word are entered into F13-1, FF-Z and FF-3 upon successive occurrences of the odd phase signals of ring counter RC-1WF-c, WF-e and WF-g, and shifted as a group into the next and successive groups of devices at successive occurrences of the even phase signals of ring counter RC-1, WF-d, WF-f and WF-h. The bits of the input data word are shifted through the shift register, group-by-group, to the last group-FF-19, FF- Zi) and FF-Zl-from Where they are exited serially from F13-22 at the successive occurrences of the even phase signals of ring counter RC3-1.

As an example of the above relationships, consider the embodiment of FIG. 1 as including an array of n+1=21+l bistable devices arranged in y:7 groups of mz3 devices per group Where n=my=3 7=2l having input means providing the true and Ithe complement representation of a multi-bit input data Word of L=15 bits and a frequency F Where F=1/ T and T :unit signal time lor time between successive bit representations, oscillator means providing a 15:2 phase clocking signal of frequency F, and a ring counter providing a m=3 2 phase clocking signal of frequency Z where Z=F/m :F/ 3 and of a unit signal time S Where S=mvT=3 T. First and successive bits-up to m=3 bits-of the input data Word of L=15 bits `are entered into lthe rst group of m=3 devicesFF-1, FF-Z and FF-S-at a frequency F at successive occurrences of said first clocking means first phase signal of said =2 phase signal with each group of mz3 bits of the input data Word then shifted into successive groups of devices `from said first group of devices-L y-2, y-1,-into the last group of devices-y=7at a frequency at successive times Tee-Tea until the bits of the input data Word are exited serially from 4the (n-l-l)th, or 22nd, device at successive occurrences of said first clocking means bthzZnd phase signal.

It is understood that suitable modifications may be made in the structure as disclosed provided such modifcations come Within the spirit and scope of the appended claims. Having now, therefore, fully illustrated and described rny invention, What I claim to be new and desire to protect -by Letters Patent is:

1. A digital signal responsive device comprising n bistable devices arranged in y groups of m devices per arranca group, each device having set and clear sides With each y of said sides having an input and an output associated therewith; first clocking means providin(r a p phase clocking signal of frequency F and a uni-t signal time T Where y T:l/F, second clochin T means eneratinfT a m hase :D D D clocking signal of frequency Z and a unit signal time HIT, input means providing the true and t e complement of a data Word of unit signal time T; circuit means coupling the true and the complement of the data word to the lirst group of devices; circuit means coupling the outputs of the devices of each group to the inputs of corresponding devices of the next successive group of devices, circuit means coupling discrete phase signals of said q phase signal to predetermined respective groups of devices, circuit means coupling discretephase signals vof said m45 phase signal to predetermined respective groups of devices, predetermined combinations of said first and second clocking signals and true and complement data word signals successively gating groups of m true and complement data Word signal representations serially into a first group'of m devices; predetermined combinations of said first and second clocking signals successively gating inparallel the groups of the m representations of the true and complement'of the data word signals from the first, 4through succeeding, and into the yth group of devices, and then gating in serial the groups of the m Vrepresentations of the .true and the complement of the data Word signals from the yth group of devices.

2. The apparatus of claim 1 whereinV said bistable declocking signal of frequency Z and a unit signal time mT;

input means providing the true and the complement of a data Word of unit signal time T; circuit means coupling the true and the complement of the data Word to a rst group of devices; circuit means coupling the outputs of 4the devices of each group to the inputs of corresponding devices of the next successive group of devices; circuit means coupling discrete phase signals or said phase vsignal to predetermined respective groups of devices, circuit means coupling discrete phase siffnals of said me phase signal to predetermined respective groups or" devices, predetermined combinations of said first and second cio-cl:- ing signals and true and complement -data'word signals gating m true and complement data word signal representationsserially into the first Vgroup of devices; predetermined combinations of said iirst and second clocking signals successively gating in parallel the representations of the true and complement of the data Word signals from the first, through succeeding, and into the ythggroup of devices, and then gating in serial the representations of the true and the complement of the data word signals from the yth group of devices and through said (n+l)th device.

5. A digital signal responsive device comprising n bisstable devices arranged in y groupsrof m devices per group, each device having set and clear sides with each of sti sides having an input and an output associated therewith:

`first clocking means providing a g5 phase clocl-:ing signal of frequency F and a unit signal time T Where T:l/F; second clocking means generating a me phase clocking signal of frequency Z and a unit signal time inT; input means providing the true and the complement of a data word of unit signal time T; circuit means coupling the true and the complement of the data wordto a first group of devices; circuit means coupling the outputs of the devices of each group to the corresponding inputs ot correil. .s spending devices of the successive group of devices; circuit means coupling discrete phase signals of said phase signal to predetermine respective groups of devices; circuit means coupling discrete phase signals of said me 5 phase signal to predetermined respective groups of devices, circuit means coupling a first and alternately successive phase signal of said mqa clocking signal to a first and successive device, respectively, of said first group of devices; predetermined combinations of said first and second clocking signals and true and complement data word fals gating m true and complement data Word signal representations serially into the first group of devices; predetermined combinations of said irst and second clocking signals successively gating in parallel the representations of the true and complement of the data Word signals from F1e iirst, through succeeding, and into the yth group of de ces, and then gating in serial the representations of the true and the complement of the data Word signals from the yth group of devices.

6. A shift register ot bistable devices, having bistable states designated the set and the clear states, comprising: n bistable devices arranged in y groups of m devices per group, each device having setV and clear sides with each of said sides having an input and output associated therewith; rst clocking means generating a p phase first clocaing signal of frequency F; second clciting means generating a ma, second clocking signal each phase of a frequency F in, input means providing the true and the complement of an input data Word of yfrequency F; circuit means coupling the true and the complement of the input data Werd to the input of the set and the clear sides, respectively of the devices of a first group of devices; circuit means coupling the ouput of the set and the clear ides of the devices of each group to the input of the set and the clear sides, respectively, of the corresponding devices oi a succeeding group of devices, means coupling each phase signal of said first clocking means to separate groups of devices; circuit means coupling each phase signal of said second clocking means to separate groups of devices; iirst and alternately successive phase signals of said second clocking means coupled to first and successive devices, respcctivcly, of said first group o devices; discrete bits of said input data word serially entered into said first group of devices at successive occurrences of said first clocking means first phase signal, said bits which are then stored in said hrst group of devices being shifted into successive groups of devices in parallel, and said bits being emitted serially from-said yth group of devices. i

7. A shift register of bistable devices, having bistable states designated the set and the clear states, comprising: n bistable devices arranged in y groups of n devices per group, each device having set and clear sides with each of said sides having an input and an output associated therewith; first clocking means generating a gb phase tirst clocking signal of `frequency F and of a unit signal time T Where T=l/F; Vsecond clocking means generating a mqb phase second clocing signal of a frequency Z and of a unit signal time S Where S:mT; input means providing the true and the complement oli an input data Word of frequency F and of a unit signal time T; circuit means 0 coupling the true and the complement of the input data Word to the inputoi the set and the clear sides, respectively, of the devices of a first group of devices; circuit means coupling Vthe output of the set and the clear sides of the devices of each group to the input of the set andthe 65 clear sides, respectively, of the corresponding device of the succeeding group of devices; means coupling each phase signal of said first clocking means to separate groups of devices; circuit means coupling each phase signal of said second clocking means to separate groups of devices; first and alternately successive phase signals of said second clocking means coupled to first and successive devices, repectvely, of said rst group of devices; discrete bits of said input data Word serially entered into said first group of devices at successive occurrences of said rst clocking 75 means first phase signal, said bits which are then stored in said first group of devices being shifted into successive groups of devices in parallel at successive times and said bits being emitted serially from said yth group of devices at successive occurrences of said first clocking means pth phase signal.

8. A shaft register of n-l-l bistable devices having bistable states designated the set and clear states, comprising: n bistable devices arranged in y groups of m devices per group, each device having set and clear sides with each of said sides having an input and an output associated therewith; first clocking means generating a 2 phase, first clocking signal of frequency F and of a unit signal time T, Where T =1/F second clocking means generating a 2m phase, second clocking signal having a unit signal time S, where S=mT; first input means providing the true and the complement of an input data Word having a unit signal time T; first circuit means coupling the true of the input data Word to the set sides of the devices of a first group of devices; second circuit means coupling the complement of the input data Word to the clear sides or the devices of said first group of devices; third circuit means coupling said first clocking means first phase signal to the clear and set sides of the devices of said first and successive alternate group of devices; first and second output gating means; fourth circuit meanscoupling said first clocking means second phase signal to the clear and set sides of the devices of second and successive alternate groups of devices, and to said first and second output gating means; first and successive alternate phase signals of said second clocking signal being coincident with successive pulses of said first clocking signal first phase; second and successive alternate phase signals of said second clocking signal being coincident with successive pulses of said first clocking signal second phase; circuit means-coupling said second clocking signal first phase to the clear and set sides of the devices of the yth group of said devices and to the clear and set sides of a first device of said first group of devices; circuit means coupling said second clocking signal second phase to the clear and set sides of the devices of the (y-l)th group of said devices; circuit means coupling said second clocking signal third phase to the clear and set sides of the (y-2)th group of said devices and to the clear and set sides of a second device of said first group of devices; circuit means coupling said second clocking signal fourth phase to the clear and set sides of the (y-3)tl1 group of said devices; the above circuit configurations repeated with circuit means coupling said second clocking signal (2m-l)th phase to the clear and set sides of the mth group of said devices and to the clear and set sides of the mth device of said first group of devices, and with circuit means coupling said second clocking signal Zmth phase to the clear and set sides of the (m-i)th group of said devices; circuit means coupling the output of the set sides of said first through the mth devices of said yth group to said first output gate; circuit means coupling the output of the clear sides of said first through the mth devices of said yth group to said second output gate; an (ml-Urb bistable device having set and clear sides with each of said sides having an input and an output associated therewith; circuit means coupling said first output gate to the input of the set side of said (n-l-l)th bistable device; circuit means coupling said second output gate to the input or the clear side of said (n+l)th bistable device; discrete bitsV of said input data Word serially entered into said first group of devices at successive occurrences of said first clocking means first phase signal, said bits Which are then stored in said first group of devices being shifted into successive groups of devices in parallel at successive times T(m-1/2), and said bits being emitted serially from said (n+1)th device at successive occurrences of said first clocking means second phase signal.

9. A shift register of n-l-l bistable devices having bistable states designated the set and clear states, comprising: n bistable devices arranged in y groups of m devices per group, each device having set and clear sides with each of said sides having an input and an output associated therewith; first clocking means generating a 2 phase, first clocking signal of frequency F and of a unit signal time T, Where T 1/F second clocking means generating a 2m phase, second clocking signal of frequency Z, Where Z=F/m, and of a unit signal time S, Where S=mT; first input means providing the true and the complement of an input data Word of L bits and frequency F; first circuit means coupling the true of the input data Word to a first group of devices; second circuit means coupling the complement of the input data Word to said first group of devices; third circuit means coupling said first clocking means first phase signal to first and successive alternate groups of devices; first and second output gating means; fourth circuit means coupling said first clocking means second phase signal to second and successive alternate groups of devices, and to said first and second output gating means, first and successive alternate phase signals of said second clocking signal being coincident with successive pulses of said first clocking signal first phase; second and successive alternate phase signals of said second clocking signal being coincident With successive pulses of said first clocking signal second phase; circuit means coupling said second clocking signal first phase to the yth group of said devices and-to a first device of said first group of devices; first and second gating means associated with the output of the set and clear sides, respectively, of each device of the yth group of devices, circuit means coupling said second clocking signal second phase to the (y-l)th group of said devices and to first and second gating means which are associated with the output of the set and clear sides, respectively, of a rst device of said yth group of devices; circuit means coupling said second clocking signal third phase to the (y-2)th group of devices and to a second device of said first group of devices; circuit means coupling said second clocking signal fourth phase yto the (y-3)th group of devices and to first and second gating means which are associated with the output of the set and clear sides, respectively, of a second device of said yth group of devices; the above circuit configurations repeated with circuit means coupling said second clocking signal (Zm-Dth phase to the mth group of devices and to the mth device of said first group or" devices, and with circuit means coupling said second clocking signal 2mth phase to the (m-l)th group of devices and to first and second gating' means associated with the output of the set and clear sides, respectively, of the mth device of said yth group of devices; circuit means coupling said first gating means which are associated with Ithe output `of the set sides of said first through the mth devices of said yth group to said first output gating means; circuit means coupling said second gating means which are associated with the output of the clear sides of said first through the mth devices of said yth group to said second output gating means; an (1H-Util bistable device having set and clear sides with each of said sides having an input and an output associated therewith; circuit means coupling said first output gating means to the input of the set side of said (n-I-Uth bistable device; circuit means coupling said second output gating means to the input of the clear side of said (n-,l-Dth bistable device; discrete bits of said input data word serially entered into said first group of devices at successive occurrences of said first clocking means first phase signal, said bits Which are then stored in said first group of devices being shifted into successive groups of devices in parallel at successive times and said bits being emitted serially from said (n+l)th `device at successive occurrences of said first clocking means second phase signal.

10. A shift register of Yrti-l-l bistable devices having bistable states designated the set and clear states, comi prising: n bistable devices arranged in y groups yof m devices per group, each device having set and clear sides with each of said sides :having an input 'and an output associated therewith; irst Yclocking means generating a 2 phase, rst clocking signal of frequency F and of a unit signal time T, Where T=vl/F; second clocking means generating a 2m phase, second clocking signal of a frequency Z where Z=F/m, and of a unit Vsignal time S, where S=mT; iirst input means providing the true and thecomplement of an input data Word of L bits and frequency F; first and second gating means associated with the input of the set sides and the clear sides, respectively, of each of said n devices, rst circuitmeans coupling the true of the input data word to said'irst gating means of a first group of devices; second circuit means coupling the complement of the input data word to said second gating means of Vsaid firstgroup of devices; third circuit means coupling said first clocking means first phase signal to said first and second gating means of said first and successive alternate groups of devices and to said second clocking means; first and second output gating means; fourth circuit means coupling said first clocking means second phase signal to said first and second gating means of second and successivey alternate groups of devices, to`

Vcircuit means Vcoupling said second clocking signal first phase -to said first and second gating means of the yth group of devices and to said irstrand second gating means of a first device of said first group of devices; rst and second gating means associated with the output ofthe t set and clear sides, respectively,` of,V each devicerof the yth group of devices; circuit means coupling said second clocking signal second phase to said first and second gating means of the (y-l)tl1 group of devices and to said first and second gating means which are associated with the output of the set and clear sides, respectively, of a first device of said yth` group of devices; circuit means coupling said second clocking signal third phase to said first and second gating means of the (y`-2)th group of said devices and to said first andV second'gating means of a second device of said first group of devices; circuit means coupling said second clocking signal fourth phase clocking signal 2mth phase to said first and second Y gating means of the (m-Dth group of devices and to said first and second gating means associated With the output of the set and clear sides, respectively, of the mth device of said yth group of devices; circuit means coupling said first gating means which are Vassociated with the output of the set sides of said first through the mth devices of said yth group to said first output gating means; circuit means coupling said second gating means Which are associated with the output of the clear sides of said first through the mth devices of said yth groupv to said second output gating means; an (n+l)th bistable device having set and clear sides with each of said sides having an input and an output associated therewith; circuit means coupling said first output gating means to the input of the set side of said (rz-l-Dth bistable device; circuit means vcoupling said second output gating means to the input of the clear side of said (n+1)tl1 bistable device; discrete bits of said input ldata word serially entered into said first group of devices at successive occurrences of said first ciocking means first phase signal,

.said bits which are then stored in said first group of devices being lshifted into successive groups of devices in parallel at successive times T (m-l/ 2), and said bits being emitted serially from said (n+1)th device at successive occurrences of said first clocking means second phase signal.

ll. A digital signal responsive device comprising a plurality of bistable devices arranged in a plurality of groups of a plurality of devices per group, each device having set and clear sides with each of said sides having an input and an output associated therewith:

-iirstclocking means providing a first clocking signal;

second clockingkmeans providing a second clocking signal;

input means providing the true and the complement signal representations of a multi-bit data word;

circuit means coupling the signal representations of the true and the complement of the data word to a irst group of, devices;

circuit means coupling the outputs of the devices of each group to the inputs of corresponding devices of theV next successive group of devices;

circuit means coupling discre'te phase signals of said iirst clocking signal to predetermined respective groups of devices; Y

circuit means coupling discrete phase signals of said second clocking signal to predetermined respective groups of devices;

predetermined combinations of said Yfirst and second clocking signals with said true and complement data Word signal representations successively gating groups of 'true and complement data Word signal representations serially into the first group of devices;

predetermined combinations of said first and second clocking signals successivelyv gating in parallel the groups ofV the signal representations of the true and complement of the data word from Vthe first, through succeeding, and into the'last group of devices;

and then gating in serialthe groups of the signal representations of thetrue and the complement of the data Word from the last group of devices.

l2. A digital signal responsive device comprising:

a plurality of bistable devices arranged in groups of no more than m devices per group,'each device having set and clear sides with each of said sides having an input and an output associated therewith;

first clocking means providing a first clocking signal of at least two phases each of frequency F and a unit signal time where T=l/F;

second clocking means providing a second clocking signal of at least 2m phases each of frequency Z and a unit signal time mT;

input means providing the true and the complement signalrepresentations of a multi-.bit data word of unit signal time T;

circuit means coupling the signal representations of the true and the complement of the data word to arfrst group of devices;

circuit means coupling the outputs of the devices of each group to the inputs of corresponding devices Vof the next successive group ofdevices;

circuit means coupling discrete phase signals of said first clocking signal to predetermined respective groups of devices;

circuit means coupling discrete phase signals of said second clocking signal to predetermined respective groups of devices;

predetermined combinations of said first and second clocking signals with said true and complement data word signal representations gating m true and coml? plement data Word signal representations serially into the first group of devices;

predetermined combinations of said first and second clocking signals successively gating in parallel m signal representations of the true and the complement of the data Word from the first, through succeeding, and into the last group of devices;

and then gating in serial the signal representations of the true and the complement of the data word from the last group of devices.

13. A digital signal responsive device comprising:

a plurality of bistable devices arranged in a plurality of groups of no more than m' devices per group, each device having set and clear sides With each of said sides having an input and an output associated therewith;

rst clocking means providing a first multi-phase clocking signal of frequency F and a unit time T Where T=l/F;

second clocking means providing a second multi-phase clocking signal of frequency Z and a unit signal time mT;

input means providing the true and the complement of a data Word of frequency F and a unit signal time T;

circuit means coupling the true and the complement signal representations of the data Word to a first group of devices;

circuit means coupling the outputs of the devices of each group to 'the corresponding inputs of corresponding devices of the next successive group of devices;

circuit means coupling discrete phase signals of said first clocking signal to predetermined respective groups of devices;

circuit means coupling discrete phase signals of said second clocking signal to predetermined respective groups of devices;

circuit means coupling the first and alternately successive phase signals of said second clocking signal to the first and successive devices, respectively, of said first group of devices;

predetermined combinations of said first and second clocking signals With said true and complement data Word signal representations gating no more than m true and complement data word signal representations serially into the first group of devices;

predetermined combinations of said first and second clocking signals successively gating in parallel the signal representations of the true and the complel ment of the data Word from the first, through succeeding, and into the last group of devices;

and then gating in serial the signal representations of the true and the complement of the data Word from the last group of devices.

14. A digial signal responsive device comprising:

a plurality of bistable devices arranged in a plurality of groups of a plurality of devices per group, each device having set and clear sides with each of said sides having an input and an output associated therewith;

first clocking means generating a multi-phase first clocking signal;

second clocking means generating a multi-phase second clocking signal;

input means providing the true and 'the complement signal representations of a multi-bit input data word;

circuit means coupling the true and the complement signal representations of the input data Word to the inputs of the set and the clear sides, respectively, of the devices of a first group of devices;

circuit means coupling the outputs of the set and the clear sides of the devices of each group to the input of the set and clear sides, respectively, of the corresponding devices of the succeeding group of devices;

circuit means coupling each phase signal of said first clocking means to separate groups of devices;

circuit means coupling each phase signal of said second clocking means to separate groups of devices;

rst and alternately successive phase signals of said second clocking means coupled to first and successive devices, respectively, of said first group of devices;

discrete signal representations of said input data Word serially entered into said first group of devices at successive occurrences of said first clocking means iirst phase signal, said discrete signal representations which are then stored in said first group of devices being shifted into successive groups of devices in parallel, and said discrete signal representations being emitted serially from said last group of devices.

References Cited by the Examiner UNITED STATES PATENTS 2,957,163 10/60 Kodis 340-174 ARTHUR GAUSS, Primary Examiner.

GEORGE N. WESTBY, Examiner. 

11. A DIGITAL SIGNAL RESPONSIVE DEVICE COMPRISING A PLURALITY OF BISTABLE DEVICES ARRANGED IN A PLURALITY OF GROUPS OF A PLURALITY OF DEVICES PER GROUP, EACH DEVICE HAVING SET AND CLEAR SIDES WITH EACH OF SAID SIDES HAVING AN INPUT AND AN OUTPUT ASSOCIATED THEREWITH: FIRST CLOCKING MEANS PROVIDING A FIRST CLOCKING SIGNAL; SECOND CLOCKING MEANS PROVIDING A SECOND CLOCKING SIGNAL; INPUT MEANS PROVIDING THE TRUE AND THE COMPLEMENT SIGNAL REPRESENTATIONS OF A MULTI-BIT DATA WORD; CIRCUIT MEANS COUPLING THE SIGNAL REPRESENTATIONS OF THE TRUE AND THE COMPLEMENT OF THE DATA WORD TO A FIRST GROUP OF DEVICES; CIRCUIT MEANS COUPLING THE OUTPUTS OF THE DEVICES OF EACH GROUP TO THE INPUTS OF CORRESPONDING DEVICES OF THE NEXT SUCCESSIVE GROUP OF DEVICES; CIRCUIT MEANS COUPLING DISCRETE PHASE SIGNALS OF SAID FIRST CLOCKING SIGNAL TO PREDETERMINED RESPECTIVE GROUPS OF DEVICES; CIRCUIT MEANS COUPLING DISCRETE PHASE SIGNALS OF SAID SECOND CLOCKING SIGNAL TO PREDETERMINED RESPECTIVE GROUPS OF DEVICES; PREDETERMINED COMBINATIONS OF SAID FIRST AND SECOND CLOCKING SIGNALS WITH SAID TRUE AND COMPLEMENT DATA WORD SIGNAL REPRESENTATIONS SUCCESSIVELY GATING GROUPS OF TRUE AND COMPLEMENT DATA WORD SIGNAL REPRESENTATIONS SERIALLY INTO THE FIRST GROUP OF DEVICES; PREDETERMINED COMBINATIONS OF SAID FIRST AND SECOND CLOCKING SIGNALS SUCCESSIVELY GATING IN PARALLEL THE GROUPS OF THE SIGNAL SUCCESSIVELY GATING IN PARALLEL THE COMPLEMENT OF THE DATA WORD FROM THE FIRST, THROUGH SUCCEEDING, AND INTO THE LAST GROUP OF DEVICES; AND THEN GATING IN SERIAL THE GROUPS OF THE SIGNAL REPRESENTATIONS OF THE TRUE AND THE COMPLEMENT OF THE DATA WORD FROM THE LAST GROUP OF DEVICES. 